1. Technical Field
The present disclosure relates to a High Voltage or HV switch configuration. The disclosure particularly, but not exclusively, relates to a HV switch configuration to be used in ultrasound apparatuses and the following description is made with reference to this field of application for convenience of explanation only.
2. Description of the Related Art
As is well known, a High Voltage or HV switch is usually realized by means of a high voltage MOS or DMOS transistor being able to manage high voltages between its drain and source terminals, as well as with respect to a substrate potential. The highest voltage value Vgs between its gate and source terminals is however limited to some volts (3V or 5V).
In particular, when the High Voltage switch is off it should be able to interrupt the passage of current independently from the voltage polarity at its ends. However, further to the connection of the body terminal to the source terminal, a junction is created between the source and drain terminals, which prevents the inversion of the polarity across the High Voltage switch without triggering a passage of current in the intrinsic diode thus created even if the relative channel is off.
To overcome this drawback, a High Voltage switch is realized by a configuration comprising two MOS or DMOS transistors being placed in series, so that the relative intrinsic diodes are biased in antiseries, i.e., with a pair of corresponding terminals, for example respective anodes, in common, as schematically shown in FIG. 1, the High Voltage switch configuration being indicated with 1.
The High Voltage switch configuration 1 comprises a first and a second DMOS transistor, DM1 and DM2 respectively, connected in series with the corresponding intrinsic diodes in antiseries. In this way, at least one intrinsic diode of the High Voltage switch configuration 1 is always inversely biased. The two DMOS transistors are N-channel HV transistors and have a common source terminal X1.
Moreover, a driving device or driver 2 is to be provided that is able to follow a turn on/off command of the High Voltage switch configuration 1 and to apply a first turn on voltage value (for example equal to 5V) between the gate and source terminals of the transistors contained in the High Voltage switch configuration 1 when it is to be turned on and a second turn off voltage value (for example equal to 0V) between the gate and source terminals of the transistors when the High Voltage switch configuration 1 is to be turned off.
In particular, the driver 2 is schematically represented in FIG. 1 by a generator Ge that connects respective common source X1 and gate X2 terminals of the DM1 and DM2 transistors. The DM1 and DM2 transistors also have drain terminals connected to an output terminal OUT and to an input terminal IN of the High Voltage switch configuration 1, respectively.
The driver 2 should provide to the common gate terminal X2 a suitable gate voltage for the DM1 and DM2 transistors, such a gate voltage should dynamically follow an input signal Vin applied to the input terminal IN of the High Voltage switch configuration 1 and able to correctly define the ON/OFF state of the High Voltage switch configuration 1 as above explained.
It has been observed that the High Voltage switch configuration 1 of FIG. 1 has a really good dynamic behavior.
In particular, in ultrasound apparatuses, a plurality of High Voltage switches are used, a HV trapezoidal waveform signal Vin being applied to their input terminals. Such a HV input signal Vin usually goes between −100V and +100V and have really fast up and down edges from 3000 to 10000 V/us, as shown for instance in FIG. 2.
In an example case of use in an ultrasound apparatus, the output terminal OUT of the High Voltage switch configuration 1 is connected to a piezoelectric transducer PZ as a Load, whereto the output signal Vout is applied, and the input terminal IN is connected to a generator of a pulsed input signal, indicated as HV pulser in FIG. 1 and able to provide a HV trapezoidal waveform as input signal Vin.
According to this example application in the ultrasound field, the equivalent capacitive value Cload of the piezoelectric transducer PZ is approximately equal to 15 pF and the corresponding saturation current Id_sat of the DM1 and DM2 transistors of the High Voltage switch configuration 1 is approximately equal to 35 mA.
Stating these values, the maximum slope of the output signal Vout at the output terminal OUT of the High Voltage switch configuration 1 and thus between the ends of the load, i.e., the piezoelectric transducer PZ, should be equal to:Slope=Id_sat/Cload=35 mA/15 pF=2333 v/us,as shown in FIG. 2 in a broken line.
From a theoretical point of view, during the positive half wave of the input signal Vin, the current would flow, within the High Voltage switch configuration 1, through the channel of the second transistor DM2 and the intrinsic body-drain diode of the first transistor DM1, being directly biased, according to the current path P1 shown in FIG. 3A in a broken line.
Analogously, during the negative half wave of the input signal Vin, the current is expected to flow, within the High Voltage switch configuration 1, through the channel of the first transistor DM1 and the intrinsic body-drain diode of the second transistor DM2, being directly biased, according to the current path P2 shown in FIG. 3B in a broken line.
In both cases, the current value flowing in the High Voltage switch configuration 1 would be limited by the saturation current Id_sat of one of the DM1 and DM2 transistors, i.e., to approximately 35 mA.